L9341 quad low side driver avance data du/dt and di/dt control pwm controlled output current short current protection and di- agnostic integrated flyback diode undervoltage shutdown overvoltage and undervoltage di- agnostic overtemperature diagnostic description the L9341 is a monolithic integrated circuit real- ized in multipower bcd-ii mixed technology. the driver is intended for inductive loads in synchro- nous pwm applications, especially for valve driv- ers. the output voltage and current rise and fall slopes du/dt and di/dt are controlled. this is advanced information on a new product now in development or undergoing evaluation. det ails are subject to ch ange without notice. march 1994 undervoltage shutdown diagnostic driver short current protection channel 1 channel 4 channel 3 channel 2 v flyth v offth comp1 comp2 i osc sdo sdi sclk res1 serial interface & pwm controll bias 7 1 15 14 8 6 13 5 11 res2 3 10 9 12 rext cs 4 out3 out4 gnd vs v s i i s cc i out1 i i out2 out3 i out4 osc c i gnd c bat d bat vcc c o1 c o2 c c o3 o4 out2 vcc 2 outs out1 di / dt & du / dt control thermal flag 220nf 10nf 10nf 10nf 10nf 10uf r ext 12.4k 10nf w block & application diagram multiwatt 15 ordering numbers: L9341v L9341h multipower bcd technology 1/10
absolute maximum ratings symbol parameter value unit v cc v cc voltage range -0.3 to 6 v v s v s voltage range -0.3 to 24 v v spmax vs voltage range for t 400ms -2 to 40 v v st schaffner transient pulses on v s see note 1 v vin input voltage range for sdi; sclk;cs;res1;res2 -0.3to v cc +0.3 v out output voltage range for all outputs: negative positive C 0.3 intern. clamped to v s v v i out output current for all outputs: negative positive C 2 + 2 a a for transient with t < 10ms negative positive C 5 5 a a schaffner transient pulses on output see note 2 v esd esd voltage capability (mil 883 c) 1500 v thermal data symbol parameter value unit r th j-case thermal resistance junction to case 3 c/w r th j-amb thermal resistance junction to ambient mounted on pc board 35 c/w t sdh thermal hysteresis 20 c t sd thermal diagnostic t j > 150 c notes: 1. schaffner transient specification: din 40839 test waveforms of the following type: 1, 2, 3a, 3b, 5 and 6. the pulses are applied to the application circuit according to fig. 3. 2. the maximum output current results from the schaffner pulses specified in note 1. pin connection (top view) L9341 2/10
electrical characteristics (unless otherwise specified: 8v v s 24v; 4.7v v cc 5.3v; C 40 c tj 150 c; i o 1a (note 3); i o 1.5a; v sp = v s for t 400ms; v outp = v out for t 400ms; r ext = 12.4k w 1%). symbol parameter test condition min. typ. max. unit i ccq v cc quiescent current all outputs off 1 3 ma i sq v s quiescent current all outputs off 14 25 ma v ccu v cc undervoltage threshold see note 4 3 4 4.7 v v ccr v cc range for res1 and res2 operation 3v r on on resistance i o = 1a t j = 125 c t j = 25 c 750 450 m w m w i o off off state output current outputs off 1.4v v o v s v outp = v sp = 40v 1 1 2.5 4 10 ma ma v outf output voltage during flyback i o = 1a output off t j = 25 c t j = 125 c v s +1.3 v s +1.1 v v i gndf current to gnd during flyback (see note 5) i o = 1a output off v s = 24v v sp = 40v 17 20 44 52 ma ma i outr reverse leakage current v sp - v o = 40v 500 m a v inh high input level of sclk, sdi, cs, res1, res2 0.7*v cc v cc +0.3 v v inl low input level of sclk, sdi, cs, res1, res2 C 0.3 0.3*vcc v v reshys hysteresis of reset inputs res1, res2 0.3 1 v i inresh input current on res1,res2 res i = h; -2v v sp 8v res i = h; 8v v sp 40v C 10 5 10 10 m a m a i in input current on sclk,sdi,cs C 2v vsp 40v C 10 10 m a v sdoh high level sdo output voltage i sdo = -1ma -2v v sp 40v 0.9*v cc v cc v v sdol low level sdo output voltage i sdo = 1ma -2v v sp 40v 0 0.4 v i sdoz sdo tristate high-z leakage current 0 v sdo v cc C 2v v sp 40v C 10 10 m a pwm duty pwm duty cycle 1/16 15/16 k f frequency accuracy constant see note 6 0.93*k fn k fn 1.07*k fn v flyth flyback diagnostic comparator threshold 40 3 v sp 3 8v v s 8v v s C 1 1.5 v s C 0.4 v v v offth off state diagnostic comparator threshold 1.5 2 v i outl output current limitation threshold see note 7 1.5 2.5 a t dpo delay time pwm signal to out. 5 15 m s s ov output voltage rise and fall slope | du/dt | (from 10 to 90% of v o ) fig. 2 1.0 10 v/ m s s oc output current rise and fall slope |di/dt| 0.1 io 1.5a (from 10 to 90% of i o ) 25 125 ma/ m s notes: 3. the mean value is i o = 1 t i o ( t ) dt 0 t ; 4. the outputs are switced off for vcc vccu. the logic is not reseted. for a reset, res1 or res2 must be used. 5. this current is measured in the gnd - terminal when one single output is in fl yback and consists of the supply current added to the value of the output current source and the leakage current of the flyback diode. this leakage current is less than 1% of the nominal flyback current. 6. the pwm frequency is defined by an external capacitor. the pwm oscillator frequency is: f pwm = f osc 32 with f osc = k f c osc 1a/v and k in = 15 10 -6 ; the range is: 300hz f pwm 3000hz. the osc pin can be alternatively driven by an external ttl / cmos signal. 7. for i out 3 i outl an internal comparator swit ches the corresponding output off for the current pwm cycle. L9341 3/10
15 clk pwm3 pwm4 pwm1 pwm2 14131211109876543210 figure 1: logic diagram of pwm generation. +12v i s i s 12v 0 1a 1a 0 0 du/dt du/dt di/dt di/dt di/dt di/dt 5% 5% internal pwm signal i i current through flyback diode current through low side switch i gnd out v out t dpo out t dpo f i f d dmos d out v s d i f output voltage v 20 mh 5 10 nf 220 nf figure 2: output switching diagram. 220 nf d1 schaffner generator 4 x 10 nf -2v to 40 v vs gnd out1 out2 out3 out4 4 x 1 nf +12v 10 uf vcc +5v figure 3: test circuit for schaffner pulses. internal clock L9341 4/10
msb 14 13 12 11 3 2 1 lsb msb 14 13 12 11 3 2 1 lsb sclk sdi sdo cs sclk sdi sdo t clcl t chcl t ch t cl t clch t chch t su t h t d t clz t oh t zch 15 14 0 0 15 cs figure 4: synchronous serial interface protocol. f clock clock frequency min. dc max. 2mhz t ch width of clock input high puls min. 200ns t cl widh of clock input low puls min. 200ns t cicl clock low before cs low min. 200ns t chcl clock high after cs low min. 200ns t clch clock low before cs high min. 200ns t chch clock high after cs high min. 200ns t ciz sdo low-z cs low min. 0ns max. 400ns t zch sdo high-z cs high max. 400ns t su sdi input setup time min. 80ns t h sdi input hold time min. 80ns t d sdo output delay time (c l = 50pf) max. 100ns t oh sdo output hold time min. 0ns L9341 5/10
bit 3 - 0 pwm1 pwm2 pwm3 pwm4 output 0000 15/16 15/16 15/16 15/16 off 0001 1/16 15/16 1/16 15/16 on 0010 2/16 14/16 2/16 14/16 on 0011 3/16 13/16 3/16 13/16 on 0100 4/16 12/16 4/16 12/16 on 0101 5/16 11/16 5/16 11/16 on 0110 6/16 10/16 6/16 10/16 on 0111 7/16 9/16 7/16 9/16 on 1000 8/16 8/16 8/16 8/16 on 1001 9/16 7/16 9/16 7/16 on 1010 10/16 6/16 10/16 6/16 on 1011 11/16 5/16 11/16 5/16 on 1100 12/16 4/16 12/16 4/16 on 1101 13/16 3/16 13/16 3/16 on 1110 14/16 2/16 14/16 2/16 on 1111 15/16 1/16 15/16 1/16 on figure 5: pwm generation function table. bit. nr. name contents 0 p10 pwm duty cycle for channel 1 / bit 0: lsb 1 p11 pwm duty cycle for channel 1 / bit 1 2 p12 pwm duty cycle for channel 1 / bit 2 3 p13 pwm duty cycle for channel 1 / bit 3 : msb 4 p20 pwm duty cycle for channel 2 / bit 0 : lsb 5 p21 pwm duty cycle for channel 2 / bit 1 : 6 p22 pwm duty cycle for channel 2 / bit 2 : 7 p23 pwm duty cycle for channel 2 / bit 3 : msb 8 p30 pwm duty cycle for channel 3 / bit 0 : lsb 9 p31 pwm duty cycle for channel 3 / bit 1 : 10 p32 pwm duty cycle for channel 3 / bit 2 : 11 p33 pwm duty cycle for channel 3 / bit 3 : msb 12 p40 pwm duty cycle for channel 4 / bit 0 : lsb 13 p41 pwm duty cycle for channel 4 / bit 1: 14 p42 pwm duty cycle for channel 4 / bit 2 : 15 p43 pwm duty cycle for channel 4 / bit 3 : msb figure 6: pwm information from microcontroller to qlsd. L9341 6/10
bit nr. name contents 0 f11 comp1 state at positive edge of pwm1 (0: v out1 > v flyth ; 1: v out1 < v flyth ) 1 f12 comp2 state at negative edge of pwm1 (1: v out1 > v offth ; 0 : v out1 < v ofth ) 2 f21 comp1 state at positive edge of pwm2 (0: v out2 > v flyth ; 1: v out2 < v flyth ) 3 f22 comp2 state at negative edge of pwm2 (1: v out2 > v ofth ; 0 : v out2 < v ofth ) 4 f31 comp1 state at positive edge of pwm3 (0: v out3 > v flyth ; 1: v out3 < v flyth ) 5 f32 comp2 state at negative edge of pwm3 (1: v out3 > v offth ; 0 : v out3 < v ofth ) 6 f41 comp1 state at positive edge of pwm4 (0: v out4 > v flyth ; 1: v out4 < v flyth ) 7 f42 comp2 state at negative edge of pwm4 (1: v out4 > voffth ; 0 : v out4 < v ofth ) 8 res1 logic state of res1 input (0: res1 = l ; 1: res1 = h) 9 res2 logic state of res2 input (0: res2 = l ; 1: res2 = h) 10 tsdf thermal diagnostic flag ( 0: overtemperature ; 1:normal ) 11 c1 current at negative edge of pwm1 ( 0: i out > i outl ; 1: i out < i outl ) 12 c2 current at negative edge of pwm2 ( 0: i out > i outl ; 1: i out < i outl ) 13 c3 current at negative edge of pwm3 ( 0: i out > i outl ; 1: i out < i outl ) 14 c4 current at negative edge of pwm4 ( 0: i out > i outl ; 1: i out < i outl ) 15 1 framing information (always 1) figure 7: diagnostic information from qlsd to microcontroller. pwm v out pwm v out i d t c t v dpo pwmon t t min sample point comp2 sample point comp1 dpo t t v pwmoff t min sample point comp2 sample point comp1 fig.1 fig.2 figure 8. fig. a fig. b note: for safty diagnostic take notice of the following conditions: t pwmon 3 t dpomax + t c + t v (see fig. a) t c = i d s ocmin t v = v outfmax s ovmin t pwmoff 3 t dpomax + t v (see fig. b) L9341 7/10
functional description the u511 is a pwm quad low side driver for in- ductive loads. the duty cycle of the internal gen- erated pwm signal is set by a microcontroller via a serial interface for each output. an output slope limitation for both dv/dt and di /dt is implemented to reduce rfi. the pwm generation is realized avoiding a simultaneous output switching. as a result, di/dt becomes smaller. integrated flyback diodes clamp the output voltage during the fly- back phase of the low side switches. the driver is protected against short circuit. an undervoltage shutdown circuit switches off all out- puts if v cc is less then v ccu . below the shutdown voltage all outputs remain in off state regardless of the input state. after each malfunction which resets the driver, only the serial link interface can reactivate the normal function. in case of overcur- rent (i out = i out1 ), an internal comparator switches the output off. the overcurrent information can be read via the serial link for each driver separately at the negative edge of the corresponding pwm signal. the interface to the microcontroller is realized with a 16 bit synchronous serial peripheral inter- face (spi). if cs is switched low, the serial link becomes active and sdo goes to low impedance. at the rising edge of the sclk signal, one of the 16 bit of data stored in a shift register appear se- quencely at sdo. these data contain the 8 error flags, the status of thermal diagnostic flag and the external reset sources res1, res2 and the over- current flgs c1...c4. the last bit is framing infor- mation (see fig. 7). at each falling edge of sclk, one of the 16 bits of data sent by the microcon- troller is transferred via the sdi input to the driver. these data contain the duty-cycle information for the internal pwm generation (4 times 4 bit). on the rising edge of cs the previously stored in- formation is transferred to the circuits. sdo be- come now high impedance and sdi is inactive. the serial interface of the qlsd is cascadable with the serial link interface of another qlsd, thus obtaining a 32 bit serial link information wich can control eight inductive loads. for a safety data transfer the takeover of data bits is only real- ized when the number of sclk - clocks is n x 16 (n 3 1). the pwm duty cycle is set by 4 bit for each out- put independently via the serial link. if all four bits for an output are zero, the output is turned off, but the error diagnosis will work correctly (see fig. 5 and 6). the pwm frequency is defined by an ex- ternal capacitor on the osc pin. rext defines through the reference current the output current slope, the diagnostic cur rent sink and the internal oscillator frequency (together with c osc ). for error diagnosis the voltage on the output is measured during the on and off state of the par- ticular output driver. upon the rising edge of the pwm signal (at this moment the power output is off and will be switched on) the status of comp1 is stored into an internal latch. on the falling edge of the pwm signal ( the power output is on and will be switched off) the status of comp2 is stored into another internal latch. this information can be read via the serial link for each output driver separately (see fig. 7). the thermal diagnostic switch the thermal flag to 0 in case of overtemperature t 3 t sd . it will be switched to 1 with the hysteresis t sdth in case of t < t sd - t sdh . to avoid male functions due to extensive noise or spikes at the supply pins v cc , v s and r ext must be blocked externally via capacitors. L9341 8/10
multiwatt15 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 5 0.197 b 2.65 0.104 c 1.6 0.063 d 1 0.039 e 0.49 0.55 0.019 0.022 f 0.66 0.75 0.026 0.030 g 1.02 1.27 1.52 0.040 0.050 0.060 g1 17.53 17.78 18.03 0.690 0.700 0.710 h1 19.6 0.772 h2 20.2 0.795 l 21.9 22.2 22.5 0.862 0.874 0.886 l1 21.7 22.1 22.5 0.854 0.870 0.886 l2 17.65 18.1 0.695 0.713 l3 17.25 17.5 17.75 0.679 0.689 0.699 l4 10.3 10.7 10.9 0.406 0.421 0.429 l7 2.65 2.9 0.104 0.114 m 4.25 4.55 4.85 0.167 0.179 0.191 m1 4.63 5.08 5.53 0.182 0.200 0.218 s 1.9 2.6 0.075 0.102 s1 1.9 2.6 0.075 0.102 dia1 3.65 3.85 0.144 0.152 L9341 9/10
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publi cation are subject to change without not ice. this publication sup ersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support dev ices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies aust ralia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united k ingdom - u.s.a. L9341 10/10
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